TSMC and Samsung commit to High-NA — and to rebuilding the photomask to make it worth it
TSMC and Samsung committed to ASML's High-NA EUV scanners, Samsung by 2028 and TSMC by 2030, closing the question of whether the leading foundries would adopt the tool. Intel is already running it. The same week all three joined an ASML initiative to move photomasks from 6-inch to 12-inch, targeting a pilot line in 2031 — because today's mask size costs High-NA about 30% of its throughput.
TSMC and Samsung committed to deploying ASML's High-NA EUV lithography systems — Samsung by 2028, TSMC by 2030 — as demand for advanced AI chips rises. Intel adopted High-NA first and is already running the tools. Separately, ahead of the SPIE BACUS conference, ASML and TSMC announced an industry initiative to move photomasks from today's 6-inch format to 12-inch, with Samsung and Intel joining; the plan targets a 12-inch mask pilot line in 2031 and advanced-node production around 2033. The reason is throughput: Intel's data presented at SPIE shows that stitching two exposures together — which current mask sizes force at High-NA field dimensions — drops scanner output from roughly 175 wafers per hour to about 125, a loss of nearly 30%.
Why it matters
For two years the open question was not whether High-NA works but whether the leading foundries would buy it. TSMC in particular had signalled it could stay on 0.33-NA EUV with multipatterning and reach comparable density at lower capital cost — a real alternative, since each High-NA scanner runs around $350M. Both committing settles that, and it settles it late enough that Intel's early bet now looks like a genuine process lead rather than an expensive detour.
The mask initiative is the more interesting half, and it is the kind of detail that gets lost. High-NA's higher numerical aperture buys resolution by halving the field it can print in one exposure. Anything larger than that half-field has to be printed twice and stitched, and stitching is what eats the 30%. So the tool the industry just committed to is one that, with today's masks, is materially slower per wafer than the tool it replaces. The 12-inch mask fixes the geometry rather than working around it — which is why three competitors who agree on very little are jointly funding a standard, and why the timeline runs to 2033.
That 2033 date is the number to hold on to. Every capacity forecast and cost-per-transistor curve built on High-NA assumes throughput that the ecosystem does not have yet and will not have for seven years.
What to watch
Whether Samsung's 2028 and TSMC's 2030 dates hold, whether the 12-inch pilot line stays on 2031, and whether Intel converts its head start into a node customers move to.
Who's involved
The sole supplier of EUV lithography machines — the critical chokepoint of leading-edge manufacturing.
The world's largest foundry; ~two-thirds market share, led 2nm (N2) volume production in Q4 2025.
IDM and emerging external foundry; brought backside power (PowerVia) to volume with 18A as its comeback bet.
Reader response
Reactions and comments are reader opinion — unverified, and never part of the newsroom's fact record.
Comments 0
No comments yet — be the first.