Leading-edge chips: where the field actually stands

Leading-edge chips carry four metrics and 9 milestones here, and it is the field where a headline tie conceals the widest real gap.

On paper the node race is a three-way draw: TSMC's N2, Samsung's SF2 and Intel's 18A all entered 2nm-class volume production during 2025, with TSMC's N2 arriving in Q4. The 'nm' label is a marketing name rather than a physical dimension, which is why the tracker reads it alongside density and share. SMIC sits at 7nm, capped by lack of EUV access.

Market share tells the real story. TSMC holds about 67% of the contract-chipmaking market by revenue, Samsung about 8%, SMIC about 6% and Intel Foundry about 1% as it ramps. That dominance compounds: volume funds the next node, and the next node wins the next generation of customers. Capital expenditure shows what staying at the frontier costs — TSMC guides around $40B a year, against Intel's roughly $18B and Samsung's roughly $15B in foundry. A single leading-edge fab runs $20–30B, which is why the list of firms that can sustain this is three names long. Research output is modest at about 569 papers a year, the signature of a field where progress is capital and manufacturing execution rather than open publication.

The enabling history is short and specific. ASML's extreme-ultraviolet machines reached volume production with TSMC's 7nm+ in 2019, unlocking everything below 7nm. Samsung shipped the first gate-all-around transistors at 3nm in 2022, the architecture now succeeding FinFET across the frontier. SK hynix made high-bandwidth memory the other scarce frontier part, leading HBM3E supply for AI accelerators from 2024. Intel brought backside power delivery to a volume node with 18A's PowerVia in late 2025, a structural change rivals are still adopting.

2026's research headline was IBM demonstrating the world's first sub-1nm logic transistor architecture — a 0.7nm 'nanostack' validated at the VLSI Symposium with functional CMOS inverters and roughly 100 billion transistors on a fingernail-sized die. Read the timeline honestly: IBM is still scaling 2nm and puts production as early as about five years out. Aggregator coverage frequently conflated this with IBM's separate Anderon quantum-chip foundry plan; they are different programs.

Intel's commercial story is the one to watch. 18A-P entered risk production in June 2026, offering roughly 9% more performance or 18% lower power, aimed squarely at external foundry customers, with volume targeted by end-2026. Reports of an Apple–Intel US manufacturing partnership sent the stock up around 9%, but neither company has confirmed scope, timing or structure, so the tracker records it as unconfirmed.

The locked milestone is 1.4nm-class volume production — TSMC A14, Intel 14A, Samsung SF1.4 — with High-NA EUV, targeted around 2028. Until a challenger closes the yield gap and pulls a large customer off TSMC's lines, the leader's advantage is more likely to widen than narrow.